Cover Points| PSL Point Name | Test name | Full Path Name | Line | Count | Status |
|---|
| debug_register_read_access_cov | tb_rtl_test_nightly_invalid_frame | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 14665 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_5_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_eof | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 778 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_eof | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_disable_in_tx | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2219 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_disable_in_tx | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_1_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_bus_monitoring | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 664 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_bus_monitoring | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr_maxima | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr_maxima | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1436786 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_10 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_18 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_counter | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 44532 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_counter | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 106043 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_command_frcrst | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1341 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_command_frcrst | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_ssp_cfg | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 40386 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_ssp_cfg | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_idle | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 436 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_idle | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_transitions_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_transitions_3 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_7_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_5_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_5_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_2_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_status_mof | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 5649 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_status_mof | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_5_6_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_5_6_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_command_ercrst | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_command_ercrst | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_tx | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 4626 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_tx | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1289 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_fd_enable | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 8229 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_fd_enable | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 3593 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_test_fst | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 17853 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_test_fst | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_ovr_frm | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1659 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_ovr_frm | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_9 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_6_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_statu | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 20761 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_statu | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_1_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_19 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_3_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 16290 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_3_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_command_cd | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 958 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_command_cd | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 16941 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_32 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_32 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_status_8_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 12494 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_status_8_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_4_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_10 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_4_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_9_6_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr_ssp_acce | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr_ssp_acce | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_8_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_status_rx_buffer_size_4096 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2347362 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_status_rx_buffer_size_4096 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_3_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_15 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_3_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_21 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_5_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_retr_limit_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1813 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_retr_limit_3 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_2_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_arb_bit | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 21 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_arb_bit | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_crc_err | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1082 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_crc_err | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 140 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_rtr_r0 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 41 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_rtr_r0 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_rx | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 279 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_rx | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_5_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_6_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 13320 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_6_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_13 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_1_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_settings_tbfb | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 40867 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_settings_tbfb | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_11 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_4_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_11 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_ack_ack | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2255 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_ack_ack | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_crc_bit | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1821 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_crc_bit | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_10 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_base_id | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2395 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_base_id | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_14 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_20 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_status_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2561 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_status_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_2_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2118 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_2_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 66390 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_3 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_scan_mode | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_scan_mode | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_5_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_2_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_9_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_12 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_frame_filter | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 39134 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_frame_filter | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_2_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_timestamp_low_high | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_timestamp_low_high | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4_6_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 15132 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4_6_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_5_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 116304 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_5_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_4_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_3_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_11 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_4_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_status_rxfr | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1000409 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_status_rxfr | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_rtr_ext_id | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 41 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_rtr_ext_id | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_restr | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 7075 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_restr | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_3_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_tx | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 234 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_tx | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_rxpe | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 16234 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_rxpe | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_14 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_f | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_f | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_transition | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_transition | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_3_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_20 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_2_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_retr_limit_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 13237 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_retr_limit_2 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txnf_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txnf_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_be | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2032 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_be | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_consistency_8_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_consistency_8_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 36350 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_512 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_512 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 8354 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_5_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_ssp_4_bits_flying | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1989 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_ssp_4_bits_flying | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_1_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_12 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 15974 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_pc_fsm_transition | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_pc_fsm_transition | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_fdrf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1797 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_fdrf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_10 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_4_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_id_extension | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 4056 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_id_extension | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_norm_fd | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 10560 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_norm_fd | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_dem | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_cmd_set_ready | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 79830 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_cmd_set_ready | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_10 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_rxbam | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1399 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_rxbam | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_15 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_4_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_eft | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1030 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_eft | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_11 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_time_tran_8_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 922 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_time_tran_8_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 4410 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_change | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 970 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_change | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_4_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 15788 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_2 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_21 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_data_bit | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 401 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_data_bit | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_5_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 51439 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_9_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_9 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_9_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_9 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 4970 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_settings_nisofd | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 3312 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_settings_nisofd | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_8_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_8_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_5_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_5_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txnf_8_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txnf_8_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_1_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_command_rrb | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 106845 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_command_rrb | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_64 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_64 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr_minima | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr_minima | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 287 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_consistency_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_consistency_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 30123 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_a | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 642 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_a | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_2_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_arb_stuff | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 21 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_arb_stuff | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_1_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_ew | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_ew | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_19 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_3_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_settings_rt | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1060 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_settings_rt | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_transitions_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_transitions_2 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rec_saturation | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rec_saturation | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 7210 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_d | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_d | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 17557 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_message_filter | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 55978 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_message_filter | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_device_id | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_device_id | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_8_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 182976 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_8_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_2_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_test_fcr | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 283558 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_test_fcr | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_1_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_byte_acce | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_byte_acce | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_bus_start | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 756 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_bus_start | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_txbhci | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 46609 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_txbhci | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_6_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_retr_limit | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 95681 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_retr_limit | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_4_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_18 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_4_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_test_sd | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 5638 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_test_sd | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_srr_rtr_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 79 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_srr_rtr_2 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_9 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 16243 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_8_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_4_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_9_6_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_3_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_13 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_3_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_3_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_dlc_can20_8_64_byte | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 461 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_dlc_can20_8_64_byte | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_16 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_1_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 3097 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_5_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_2_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_3_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 35873 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_3_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_10 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_5_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_128 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_128 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txpe | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 295898 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txpe | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_3_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_12 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_3_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_ew | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_ew | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_test_ignore | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 20108 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_test_ignore | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_23 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_rxne | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_rxne | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 4504 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_4_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_17 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_4_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_14 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_1_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_2_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_5_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_overload | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1997 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_overload | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_11 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_counter | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 116080 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_counter | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_2_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_self_test | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 649 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_self_test | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_2_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 16952 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_2_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_status_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 5736 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_status_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_byte_enable | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_byte_enable | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_5_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_1_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_cmd_set_abort | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 11503 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_cmd_set_abort | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_buf_empty_read | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_buf_empty_read | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_9 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_status_rx_buffer_size_128 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 47410 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_rx_status_rx_buffer_size_128 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_3_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 70900 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_3_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_time_tran | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 7121 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_time_tran | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 31342 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_7_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_pex | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_pex | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txnf_6_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txnf_6_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_consistency_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_consistency_2 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 34583 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_2_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_1_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_transitions_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_transitions_4 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_6_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 143725 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_6_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_1_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_err_frm | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_err_frm | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_cmd_set_empty | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 22308 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_cmd_set_empty | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_of | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 4987 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_of | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_sof | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_sof | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_hazard | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_txt_buffer_hazard | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_1_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_srr_rtr | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 82 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_srr_rtr | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_fault_state | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_fault_state | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_3_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_7_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_no_sof_tx | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_no_sof_tx | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_one_shot | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 315 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_one_shot | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_b | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 11481 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_b | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 11216 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 99221 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_priority_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_filters_mask | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 216531 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_frame_filters_mask | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_loopback | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 33569 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_loopback | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_2_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_ide | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 41 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_alc_ide | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_status_6_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 7780 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_status_6_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_2_6_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 16912 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_2_6_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_1_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_6_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 9018 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_4_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_4_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_stuff_in_data | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1799 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_stuff_in_data | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txnf_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_status_txnf_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_ctrl_form | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 391 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_ctrl_form | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_rx | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 4336 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_rx | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 2673 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_5 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_5 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_8_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_txt_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_7_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_trv_delay | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 27185 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_trv_delay | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 27524 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_8 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_test | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_test | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_3_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_data_set_9 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_12 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr_fd | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 5250 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_btr_fd | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_4_6 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_rst | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_rst | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_glitch_filtering | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_glitch_filtering | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_17 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_3_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_3_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_9 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_2_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_5_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_7 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_time_tran_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 903 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_time_tran_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 4051 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_11 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_8_1_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_single_bus_node | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_single_bus_node | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_from_intermission | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 1749 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_from_intermission | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_4096 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_4096 | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_consistency_4_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_tx_arb_consistency_4_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 43494 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_13 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_4_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_6_22 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_4_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_ctrl_bit | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 411 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_err_capt_ctrl_bit | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_5_2_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_5_2_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_6_16 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_4_2 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_15 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_7_9_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_rxf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_rxf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 17214 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_8_9_1 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_5_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_5_4 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_rxne | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_int_rxne | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 11881 | covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_8_2_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_3_6_txt_buf | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 49142 | covered |
| debug_register_read_access_cov | tb_rtl_test_nightly_mode_txbbm_3_6_txt_buf | ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_2_3 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |
| debug_register_read_access_cov | tb_rtl_test_compliance_full_typ_iso_7_1_10 | ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).debug_register_read_access_cov | 3720 | 0 | not covered |