GHDL PSL Functional coverage report

Filename	Covered	Not-Covered	Functional coverage	Passed	Failed	Assertions passed
_status_read_access_cov_3531	194	327	37.2%	0	0	NA

Cover Points
PSL Point Name Test name Full Path Name Line Count Status
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_5_6_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 30 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_5_6_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_txpe ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 125795 covered
status_read_access_cov tb_rtl_test_nightly_status_txpe ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 20 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_2_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_one_shot ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 5886 covered
status_read_access_cov tb_rtl_test_nightly_one_shot ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_1_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_scan_mode ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_scan_mode ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_3_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 506 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_3_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1171 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 30 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_5 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_cmd_set_abort ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1216 covered
status_read_access_cov tb_rtl_test_nightly_tx_cmd_set_abort ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_transitions_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 25988 covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_transitions_2 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_counter ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11800 covered
status_read_access_cov tb_rtl_test_nightly_tx_counter ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 30 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_5_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_txnf_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 13 covered
status_read_access_cov tb_rtl_test_nightly_status_txnf_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_7_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_rxne ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 487 covered
status_read_access_cov tb_rtl_test_nightly_status_rxne ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_1_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_3_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_3_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_ssp_cfg ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 37600 covered
status_read_access_cov tb_rtl_test_nightly_ssp_cfg ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 852 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_ctrl_bit ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_ctrl_bit ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_ew ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 20 covered
status_read_access_cov tb_rtl_test_nightly_status_ew ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_time_tran ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 32328 covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_time_tran ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 6 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_9 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_2_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 35 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_2_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 236 covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_time_tran_8_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2665 covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_time_tran_8_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_2_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_17 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_rst ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_mode_rst ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_12 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_4_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_byte_enable ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_byte_enable ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_11 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4_6_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 20706 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4_6_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 715 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rx_statu ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1560 covered
status_read_access_cov tb_rtl_test_nightly_rx_statu ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 25 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_4_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_9_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_hazard ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 322926 covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_hazard ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_3_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_2_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_3_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_timestamp_low_high ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_timestamp_low_high ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_tx ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_int_tx ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 786 covered
status_read_access_cov tb_rtl_test_nightly_mode_frame_filter ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_frame_filter ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_single_bus_node ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 56303 covered
status_read_access_cov tb_rtl_test_nightly_single_bus_node ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_self_test ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 7 covered
status_read_access_cov tb_rtl_test_nightly_mode_self_test ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 417 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_22 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_16 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_5_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_8_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_sof ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 943 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_sof ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_13 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_2_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_stuff_in_data ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 120 covered
status_read_access_cov tb_rtl_test_nightly_stuff_in_data ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_1_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_rxne ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_rxne ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_10 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_512 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_512 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_loopback ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 34624 covered
status_read_access_cov tb_rtl_test_nightly_mode_loopback ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_15 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_5_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_bus_monitoring ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 3425 covered
status_read_access_cov tb_rtl_test_nightly_mode_bus_monitoring ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 996 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_4_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_4_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_1_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_consistency_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1163 covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_consistency_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_16 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_fault_state ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_fault_state ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_2_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_4_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_5_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_13 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_change ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 29293 covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_change ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_bus_start ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 37 covered
status_read_access_cov tb_rtl_test_nightly_bus_start ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 42 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_10 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_9 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_9_6_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_4_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_9_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_alc_srr_rtr ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4121 covered
status_read_access_cov tb_rtl_test_nightly_alc_srr_rtr ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_9_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rx_buf_empty_read ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rx_buf_empty_read ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_device_id ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_device_id ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_status_8_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 53134 covered
status_read_access_cov tb_rtl_test_nightly_tx_status_8_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_23 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_5_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_glitch_filtering ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_glitch_filtering ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_17 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_d ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_nightly_int_d ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_f ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_f ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_3_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_2_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_12 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_1_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_a ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 7202 covered
status_read_access_cov tb_rtl_test_nightly_int_a ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_3_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_11 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_overload ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 721 covered
status_read_access_cov tb_rtl_test_nightly_overload ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11826 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 477 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_3_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_pc_fsm_transition ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 69172 covered
status_read_access_cov tb_rtl_test_nightly_pc_fsm_transition ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_14 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_4_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_4_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_6_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_9 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_pex ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 31981 covered
status_read_access_cov tb_rtl_test_nightly_mode_pex ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_txnf_6_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 19 covered
status_read_access_cov tb_rtl_test_nightly_status_txnf_6_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_4_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_alc_srr_rtr_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4 covered
status_read_access_cov tb_rtl_test_nightly_alc_srr_rtr_2 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 6182 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_3_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_3_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_9 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_4_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_ew ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_ew ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_fdrf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_fdrf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_1_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 21585 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 976 covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_transitions_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 146481 covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_transitions_3 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_2_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_arb_stuff ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 672 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_arb_stuff ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_5_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 30 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_5_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_be ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 161 covered
status_read_access_cov tb_rtl_test_nightly_int_be ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1439 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_err_frm ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1511 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_err_frm ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_cmd_set_empty ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 848 covered
status_read_access_cov tb_rtl_test_nightly_tx_cmd_set_empty ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_status_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 16324 covered
status_read_access_cov tb_rtl_test_nightly_tx_status_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_6_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_6_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_1_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_frame_test_ignore ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11046 covered
status_read_access_cov tb_rtl_test_nightly_frame_test_ignore ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_3_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_14 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_idle ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 195 covered
status_read_access_cov tb_rtl_test_nightly_status_idle ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_2_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_transition ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 182 covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_transition ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_20 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rx_counter ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11811 covered
status_read_access_cov tb_rtl_test_nightly_rx_counter ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 15 covered
status_read_access_cov tb_rtl_test_nightly_rx_status_rxfr ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rx_status_rxfr ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_ack_ack ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 719 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_ack_ack ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_11 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_crc_bit ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 832 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_crc_bit ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rx_settings_rt ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4984 covered
status_read_access_cov tb_rtl_test_nightly_rx_settings_rt ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 3 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_5_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_32 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_32 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_4_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_4_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr_maxima ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr_maxima ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_12 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_5_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_5_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_2_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_3_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr_ssp_acce ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr_ssp_acce ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_3_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_txnf_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 7 covered
status_read_access_cov tb_rtl_test_nightly_status_txnf_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_10 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_1_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_15 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_5_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_11 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_9 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_21 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_9 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rx_status_rx_buffer_size_4096 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 49004 covered
status_read_access_cov tb_rtl_test_nightly_rx_status_rx_buffer_size_4096 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 611 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 148 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 472 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_10 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_3_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_command_cd ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 363 covered
status_read_access_cov tb_rtl_test_nightly_command_cd ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 3 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_10 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_8_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_3_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 998 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_3_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2349 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_crc_err ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_crc_err ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 716 covered
status_read_access_cov tb_rtl_test_nightly_tx_status_6_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 69011 covered
status_read_access_cov tb_rtl_test_nightly_tx_status_6_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_time_tran_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11232 covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_time_tran_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_4_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_5_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_arb_bit ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 942 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_arb_bit ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_4_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_settings_nisofd ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 3081 covered
status_read_access_cov tb_rtl_test_nightly_settings_nisofd ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_settings_tbfb ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 28252 covered
status_read_access_cov tb_rtl_test_nightly_settings_tbfb ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_from_intermission ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1881 covered
status_read_access_cov tb_rtl_test_nightly_tx_from_intermission ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 33 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_ovr_frm ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_ovr_frm ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_2_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_ssp_4_bits_flying ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 371 covered
status_read_access_cov tb_rtl_test_nightly_ssp_4_bits_flying ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 44 covered
status_read_access_cov tb_rtl_test_nightly_command_frcrst ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 121 covered
status_read_access_cov tb_rtl_test_nightly_command_frcrst ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_alc_rtr_r0 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 3600 covered
status_read_access_cov tb_rtl_test_nightly_alc_rtr_r0 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_status_rx ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 208 covered
status_read_access_cov tb_rtl_test_nightly_status_rx ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 470 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_2 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1218 covered
status_read_access_cov tb_rtl_test_nightly_status_txnf_8_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 25 covered
status_read_access_cov tb_rtl_test_nightly_status_txnf_8_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_restr ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 550 covered
status_read_access_cov tb_rtl_test_nightly_mode_restr ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_1_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_19 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_invalid_frame ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1205 covered
status_read_access_cov tb_rtl_test_nightly_invalid_frame ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 10 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_data_bit ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 941 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_data_bit ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_byte_acce ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11368 covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_byte_acce ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_1_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_frame_test_fcr ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 121068 covered
status_read_access_cov tb_rtl_test_nightly_frame_test_fcr ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 32872 covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_8_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_8_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_5_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_4096 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_4096 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_2_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 310 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_2_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1220 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_retr_limit_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11409 covered
status_read_access_cov tb_rtl_test_nightly_retr_limit_2 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 6 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_7_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_fd_enable ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2220 covered
status_read_access_cov tb_rtl_test_nightly_mode_fd_enable ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_command_ercrst ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_command_ercrst ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_18 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_2_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_frame_test_sd ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 40844 covered
status_read_access_cov tb_rtl_test_nightly_frame_test_sd ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 10 covered
status_read_access_cov tb_rtl_test_nightly_alc_base_id ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 90 covered
status_read_access_cov tb_rtl_test_nightly_alc_base_id ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 5658 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_1_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_message_filter ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_message_filter ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rec_saturation ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 481 covered
status_read_access_cov tb_rtl_test_nightly_rec_saturation ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4 covered
status_read_access_cov tb_rtl_test_nightly_frame_filters_mask ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 14354 covered
status_read_access_cov tb_rtl_test_nightly_frame_filters_mask ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_6_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_transitions_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11816 covered
status_read_access_cov tb_rtl_test_nightly_txt_buffer_transitions_4 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 16 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_2_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_8_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_8_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 379 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 954 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_2_6_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 505 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_2_6_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1217 covered
status_read_access_cov tb_rtl_test_nightly_alc_ide ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1358 covered
status_read_access_cov tb_rtl_test_nightly_alc_ide ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2032 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_3 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4701 covered
status_read_access_cov tb_rtl_test_nightly_dlc_can20_8_64_byte ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1162 covered
status_read_access_cov tb_rtl_test_nightly_dlc_can20_8_64_byte ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_1_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_18 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 7305 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_4_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 242 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_4_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_ctrl_form ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 4 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_ctrl_form ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_rxpe ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 20 covered
status_read_access_cov tb_rtl_test_nightly_status_rxpe ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_status_tx ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 237 covered
status_read_access_cov tb_rtl_test_nightly_status_tx ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_1_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_consistency_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1154 covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_consistency_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11 covered
status_read_access_cov tb_rtl_test_nightly_frame_test_fst ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 20355 covered
status_read_access_cov tb_rtl_test_nightly_frame_test_fst ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 9197 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_7_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_retr_limit_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 3184 covered
status_read_access_cov tb_rtl_test_nightly_retr_limit_3 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_rxbam ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_rxbam ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_7_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_norm_fd ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 32804 covered
status_read_access_cov tb_rtl_test_nightly_err_norm_fd ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 118 covered
status_read_access_cov tb_rtl_test_nightly_mode_test ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_test ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_19 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_9 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_3_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr_fd ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr_fd ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 18661 covered
status_read_access_cov tb_rtl_test_nightly_status_eft ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1011 covered
status_read_access_cov tb_rtl_test_nightly_status_eft ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_trv_delay ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2399 covered
status_read_access_cov tb_rtl_test_nightly_trv_delay ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 108 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_1_7 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_5_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 30 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_5_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_rx ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_int_rx ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 789 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_2_5 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_15 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_21 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_5_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_cmd_set_ready ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 960 covered
status_read_access_cov tb_rtl_test_nightly_tx_cmd_set_ready ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_4_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_dem ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_10 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_alc_id_extension ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 209 covered
status_read_access_cov tb_rtl_test_nightly_alc_id_extension ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 9490 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_6_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 298 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_6_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 715 covered
status_read_access_cov tb_rtl_test_nightly_command_rrb ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 13267 covered
status_read_access_cov tb_rtl_test_nightly_command_rrb ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 100 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_4_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_3_6_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1505 covered
status_read_access_cov tb_rtl_test_nightly_mode_txbbm_3_6_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 3526 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_9_6_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_4_4 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_disable_in_tx ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_nightly_disable_in_tx ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1036 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_13 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_3_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_2_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_txt_2_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_3_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_alc_rtr_ext_id ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 3080 covered
status_read_access_cov tb_rtl_test_nightly_alc_rtr_ext_id ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_tx_status_4_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 29058 covered
status_read_access_cov tb_rtl_test_nightly_tx_status_4_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_rxf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_rxf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr_minima ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_btr_minima ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_9_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_9_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_no_sof_tx ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2446 covered
status_read_access_cov tb_rtl_test_nightly_no_sof_tx ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_nightly_rx_status_rx_buffer_size_128 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2875 covered
status_read_access_cov tb_rtl_test_nightly_rx_status_rx_buffer_size_128 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 41 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_5_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_7_10 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_14 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_5_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_retr_limit ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 14893 covered
status_read_access_cov tb_rtl_test_nightly_retr_limit ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_err_capt_eof ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 679 covered
status_read_access_cov tb_rtl_test_nightly_err_capt_eof ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_6_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_b ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_b ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_8 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_20 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_3_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_6_11 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_2_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_2_11 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_8_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_data_set_6 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_1_12 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_of ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 2 covered
status_read_access_cov tb_rtl_test_nightly_int_of ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1160 covered
status_read_access_cov tb_rtl_test_nightly_rx_status_mof ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_rx_status_mof ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_64 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_64 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_128 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_128 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_8_8_1_1 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_5_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_priority_5_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_consistency_8_txt_buf ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1141 covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_consistency_8_txt_buf ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 11 covered
status_read_access_cov tb_rtl_test_compliance_full_typ_iso_7_8_5_3 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_txbhci ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_int_txbhci ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 0 not covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_consistency_2 ..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 1267 covered
status_read_access_cov tb_rtl_test_nightly_tx_arb_consistency_2 ..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov 3531 13 covered

Cover Points
PSL Point Name	Test name	Full Path Name	Line	Count	Status
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_5_6_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	30	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_5_6_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_txpe	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	125795	covered
status_read_access_cov	tb_rtl_test_nightly_status_txpe	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	20	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_2_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_one_shot	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	5886	covered
status_read_access_cov	tb_rtl_test_nightly_one_shot	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_1_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_scan_mode	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_scan_mode	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_3_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	506	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_3_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1171	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	30	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_5	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_cmd_set_abort	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1216	covered
status_read_access_cov	tb_rtl_test_nightly_tx_cmd_set_abort	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_transitions_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	25988	covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_transitions_2	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_counter	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11800	covered
status_read_access_cov	tb_rtl_test_nightly_tx_counter	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	30	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_5_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_txnf_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	13	covered
status_read_access_cov	tb_rtl_test_nightly_status_txnf_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_7_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_rxne	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	487	covered
status_read_access_cov	tb_rtl_test_nightly_status_rxne	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_1_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_3_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_3_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_ssp_cfg	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	37600	covered
status_read_access_cov	tb_rtl_test_nightly_ssp_cfg	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	852	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_ctrl_bit	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_ctrl_bit	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_ew	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	20	covered
status_read_access_cov	tb_rtl_test_nightly_status_ew	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_time_tran	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	32328	covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_time_tran	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	6	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_9	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_2_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	35	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_2_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	236	covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_time_tran_8_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2665	covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_time_tran_8_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_2_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_17	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_rst	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_mode_rst	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_12	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_4_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_byte_enable	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_byte_enable	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_11	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4_6_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	20706	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4_6_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	715	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_rx_statu	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1560	covered
status_read_access_cov	tb_rtl_test_nightly_rx_statu	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	25	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_4_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_9_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_hazard	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	322926	covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_hazard	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_3_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_2_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_3_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_timestamp_low_high	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_timestamp_low_high	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_tx	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_int_tx	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	786	covered
status_read_access_cov	tb_rtl_test_nightly_mode_frame_filter	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_frame_filter	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_single_bus_node	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	56303	covered
status_read_access_cov	tb_rtl_test_nightly_single_bus_node	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_self_test	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	7	covered
status_read_access_cov	tb_rtl_test_nightly_mode_self_test	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	417	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_22	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_16	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_5_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_8_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_sof	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	943	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_sof	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_13	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_2_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_stuff_in_data	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	120	covered
status_read_access_cov	tb_rtl_test_nightly_stuff_in_data	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_1_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_rxne	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_rxne	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_10	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_512	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_512	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_loopback	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	34624	covered
status_read_access_cov	tb_rtl_test_nightly_mode_loopback	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_15	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_5_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_bus_monitoring	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	3425	covered
status_read_access_cov	tb_rtl_test_nightly_mode_bus_monitoring	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	996	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_4_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_4_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_1_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_consistency_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1163	covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_consistency_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_16	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_fault_state	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_fault_state	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_2_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_4_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_5_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_13	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_change	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	29293	covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_change	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_bus_start	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	37	covered
status_read_access_cov	tb_rtl_test_nightly_bus_start	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	42	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_10	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_9	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_9_6_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_4_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_9_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_alc_srr_rtr	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4121	covered
status_read_access_cov	tb_rtl_test_nightly_alc_srr_rtr	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_9_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_rx_buf_empty_read	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_rx_buf_empty_read	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_device_id	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_device_id	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_status_8_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	53134	covered
status_read_access_cov	tb_rtl_test_nightly_tx_status_8_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_23	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_5_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_glitch_filtering	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_glitch_filtering	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_17	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_d	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_nightly_int_d	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_f	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_f	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_3_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_2_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_12	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_1_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_a	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	7202	covered
status_read_access_cov	tb_rtl_test_nightly_int_a	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_3_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_11	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_overload	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	721	covered
status_read_access_cov	tb_rtl_test_nightly_overload	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11826	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	477	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_3_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_pc_fsm_transition	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	69172	covered
status_read_access_cov	tb_rtl_test_nightly_pc_fsm_transition	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_14	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_4_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_4_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_6_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_9	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_pex	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	31981	covered
status_read_access_cov	tb_rtl_test_nightly_mode_pex	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_txnf_6_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	19	covered
status_read_access_cov	tb_rtl_test_nightly_status_txnf_6_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_4_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_alc_srr_rtr_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4	covered
status_read_access_cov	tb_rtl_test_nightly_alc_srr_rtr_2	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	6182	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_3_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_3_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_9	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_4_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_ew	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_ew	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_fdrf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_fdrf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_1_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	21585	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	976	covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_transitions_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	146481	covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_transitions_3	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_2_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_arb_stuff	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	672	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_arb_stuff	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_5_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	30	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_5_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_be	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	161	covered
status_read_access_cov	tb_rtl_test_nightly_int_be	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1439	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_err_frm	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1511	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_err_frm	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_cmd_set_empty	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	848	covered
status_read_access_cov	tb_rtl_test_nightly_tx_cmd_set_empty	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_status_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	16324	covered
status_read_access_cov	tb_rtl_test_nightly_tx_status_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_6_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_6_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_1_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_frame_test_ignore	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11046	covered
status_read_access_cov	tb_rtl_test_nightly_frame_test_ignore	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_3_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_14	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_idle	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	195	covered
status_read_access_cov	tb_rtl_test_nightly_status_idle	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_2_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_transition	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	182	covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_transition	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_20	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_rx_counter	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11811	covered
status_read_access_cov	tb_rtl_test_nightly_rx_counter	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	15	covered
status_read_access_cov	tb_rtl_test_nightly_rx_status_rxfr	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_rx_status_rxfr	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_ack_ack	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	719	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_ack_ack	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_11	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_crc_bit	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	832	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_crc_bit	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_rx_settings_rt	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4984	covered
status_read_access_cov	tb_rtl_test_nightly_rx_settings_rt	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	3	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_5_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_32	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_32	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_4_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_4_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr_maxima	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr_maxima	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_12	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_5_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_5_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_2_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_3_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr_ssp_acce	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr_ssp_acce	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_3_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_txnf_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	7	covered
status_read_access_cov	tb_rtl_test_nightly_status_txnf_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_10	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_1_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_15	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_5_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_11	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_9	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_21	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_9	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_rx_status_rx_buffer_size_4096	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	49004	covered
status_read_access_cov	tb_rtl_test_nightly_rx_status_rx_buffer_size_4096	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	611	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	148	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	472	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_10	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_3_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_command_cd	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	363	covered
status_read_access_cov	tb_rtl_test_nightly_command_cd	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	3	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_10	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_8_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_3_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	998	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_3_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2349	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_crc_err	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_crc_err	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	716	covered
status_read_access_cov	tb_rtl_test_nightly_tx_status_6_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	69011	covered
status_read_access_cov	tb_rtl_test_nightly_tx_status_6_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_time_tran_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11232	covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_time_tran_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_4_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_5_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_arb_bit	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	942	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_arb_bit	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_4_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_settings_nisofd	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	3081	covered
status_read_access_cov	tb_rtl_test_nightly_settings_nisofd	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_settings_tbfb	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	28252	covered
status_read_access_cov	tb_rtl_test_nightly_settings_tbfb	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_from_intermission	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1881	covered
status_read_access_cov	tb_rtl_test_nightly_tx_from_intermission	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	33	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_ovr_frm	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_ovr_frm	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_2_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_ssp_4_bits_flying	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	371	covered
status_read_access_cov	tb_rtl_test_nightly_ssp_4_bits_flying	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	44	covered
status_read_access_cov	tb_rtl_test_nightly_command_frcrst	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	121	covered
status_read_access_cov	tb_rtl_test_nightly_command_frcrst	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_alc_rtr_r0	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	3600	covered
status_read_access_cov	tb_rtl_test_nightly_alc_rtr_r0	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_status_rx	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	208	covered
status_read_access_cov	tb_rtl_test_nightly_status_rx	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	470	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_2	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1218	covered
status_read_access_cov	tb_rtl_test_nightly_status_txnf_8_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	25	covered
status_read_access_cov	tb_rtl_test_nightly_status_txnf_8_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_restr	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	550	covered
status_read_access_cov	tb_rtl_test_nightly_mode_restr	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_1_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_19	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_invalid_frame	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1205	covered
status_read_access_cov	tb_rtl_test_nightly_invalid_frame	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	10	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_data_bit	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	941	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_data_bit	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_byte_acce	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11368	covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_byte_acce	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_1_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_frame_test_fcr	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	121068	covered
status_read_access_cov	tb_rtl_test_nightly_frame_test_fcr	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	32872	covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_8_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_priority_8_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_5_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_4096	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_rx_rxb_size_4096	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_2_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	310	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_2_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1220	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_retr_limit_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11409	covered
status_read_access_cov	tb_rtl_test_nightly_retr_limit_2	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	6	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_7_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_fd_enable	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2220	covered
status_read_access_cov	tb_rtl_test_nightly_mode_fd_enable	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_command_ercrst	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_command_ercrst	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_18	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_2_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_frame_test_sd	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	40844	covered
status_read_access_cov	tb_rtl_test_nightly_frame_test_sd	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	10	covered
status_read_access_cov	tb_rtl_test_nightly_alc_base_id	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	90	covered
status_read_access_cov	tb_rtl_test_nightly_alc_base_id	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	5658	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_1_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_message_filter	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_message_filter	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_rec_saturation	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	481	covered
status_read_access_cov	tb_rtl_test_nightly_rec_saturation	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4	covered
status_read_access_cov	tb_rtl_test_nightly_frame_filters_mask	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	14354	covered
status_read_access_cov	tb_rtl_test_nightly_frame_filters_mask	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_6_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_transitions_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11816	covered
status_read_access_cov	tb_rtl_test_nightly_txt_buffer_transitions_4	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	16	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_2_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_8_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_8_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	379	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	954	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_2_6_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	505	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_2_6_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1217	covered
status_read_access_cov	tb_rtl_test_nightly_alc_ide	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1358	covered
status_read_access_cov	tb_rtl_test_nightly_alc_ide	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2032	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_3	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4701	covered
status_read_access_cov	tb_rtl_test_nightly_dlc_can20_8_64_byte	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1162	covered
status_read_access_cov	tb_rtl_test_nightly_dlc_can20_8_64_byte	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_1_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_18	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	7305	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_4_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	242	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_4_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_ctrl_form	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	4	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_ctrl_form	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_rxpe	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	20	covered
status_read_access_cov	tb_rtl_test_nightly_status_rxpe	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_status_tx	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	237	covered
status_read_access_cov	tb_rtl_test_nightly_status_tx	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_1_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_consistency_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1154	covered
status_read_access_cov	tb_rtl_test_nightly_tx_arb_consistency_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	11	covered
status_read_access_cov	tb_rtl_test_nightly_frame_test_fst	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	20355	covered
status_read_access_cov	tb_rtl_test_nightly_frame_test_fst	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	9197	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_7_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_retr_limit_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	3184	covered
status_read_access_cov	tb_rtl_test_nightly_retr_limit_3	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_rxbam	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_rxbam	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_7_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_norm_fd	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	32804	covered
status_read_access_cov	tb_rtl_test_nightly_err_norm_fd	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	118	covered
status_read_access_cov	tb_rtl_test_nightly_mode_test	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_test	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_19	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_9	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_8_3_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_1_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr_fd	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr_fd	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	18661	covered
status_read_access_cov	tb_rtl_test_nightly_status_eft	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1011	covered
status_read_access_cov	tb_rtl_test_nightly_status_eft	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_trv_delay	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2399	covered
status_read_access_cov	tb_rtl_test_nightly_trv_delay	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	108	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_1_7	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_5_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	30	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_5_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_rx	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_int_rx	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	789	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_2_5	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_15	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_data_set_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_21	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_5_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tx_cmd_set_ready	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	960	covered
status_read_access_cov	tb_rtl_test_nightly_tx_cmd_set_ready	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_4_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_dem	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_10	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_alc_id_extension	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	209	covered
status_read_access_cov	tb_rtl_test_nightly_alc_id_extension	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	9490	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_6_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	298	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_6_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	715	covered
status_read_access_cov	tb_rtl_test_nightly_command_rrb	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	13267	covered
status_read_access_cov	tb_rtl_test_nightly_command_rrb	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	100	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_4_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_3_6_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1505	covered
status_read_access_cov	tb_rtl_test_nightly_mode_txbbm_3_6_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	3526	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_9_6_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_4_4	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_disable_in_tx	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_nightly_disable_in_tx	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1036	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_13	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_3_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_2_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_tst_mem_acc_txt_2_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_3_3	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_alc_rtr_ext_id	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	3080	covered
status_read_access_cov	tb_rtl_test_nightly_alc_rtr_ext_id	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2	covered
status_read_access_cov	tb_rtl_test_nightly_tx_status_4_txt_buf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	29058	covered
status_read_access_cov	tb_rtl_test_nightly_tx_status_4_txt_buf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_rxf	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_rxf	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr_minima	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_btr_minima	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_9_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_9_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_no_sof_tx	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2446	covered
status_read_access_cov	tb_rtl_test_nightly_no_sof_tx	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_nightly_rx_status_rx_buffer_size_128	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	2875	covered
status_read_access_cov	tb_rtl_test_nightly_rx_status_rx_buffer_size_128	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	41	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_5_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_7_10	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_14	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_5_6	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_retr_limit	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	14893	covered
status_read_access_cov	tb_rtl_test_nightly_retr_limit	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_eof	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	679	covered
status_read_access_cov	tb_rtl_test_nightly_err_capt_eof	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	1	covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_6_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_b	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_nightly_int_b	..tb_top_ctu_can_fd(tb).ctu_can_fd_vip_inst@ctu_can_fd_vip(behav).feature_test_agent_gen.feature_test_agent_inst@feature_test_agent(tb).test_node_inst@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_8	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_20	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_8_3_2	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_6_11	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_8_2_1	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered
status_read_access_cov	tb_rtl_test_compliance_full_typ_iso_7_2_11	..tb_top_ctu_can_fd(tb).dut@can_top_level(rtl).memory_registers_inst@memory_registers(rtl).control_registers_reg_map_comp@control_registers_reg_map(rtl).status_read_access_cov	3531	0	not covered

Assertions
PSL Point Name Test name Full Path Name Line Count Status