NVC code coverage report
Hierarchy:
CTU_CAN_FD_TB
TB_TOP_CTU_CAN_FD
DUT
RST_SYNC_INST
MEMORY_REGISTERS_INST
TXTB_PORT_A_CS_GEN(0)
TXTB_PORT_A_CS_GEN(1)
TXTB_PORT_A_CS_GEN(2)
TXTB_PORT_A_CS_GEN(3)
TXTB_PORT_A_CS_GEN(4)
TXTB_PORT_A_CS_GEN(5)
TXTB_PORT_A_CS_GEN(6)
TXTB_PORT_A_CS_GEN(7)
CLK_GATE_CONTROL_REGS_COMP
G_TECH_ASIC
G_TECH_FPGA
CLK_GATE_TEST_REGS_COMP
G_TECH_ASIC
G_TECH_FPGA
CONTROL_REGISTERS_REG_MAP_COMP
ADDRESS_DECODER_CONTROL_REGISTERS_COMP
ADDR_DEC_GEN(0)
ADDR_DEC_GEN(1)
ADDR_DEC_GEN(2)
ADDR_DEC_GEN(3)
ADDR_DEC_GEN(4)
ADDR_DEC_GEN(5)
ADDR_DEC_GEN(6)
ADDR_DEC_GEN(7)
ADDR_DEC_GEN(8)
ADDR_DEC_GEN(9)
ADDR_DEC_GEN(10)
ADDR_DEC_GEN(11)
ADDR_DEC_GEN(12)
ADDR_DEC_GEN(13)
ADDR_DEC_GEN(14)
ADDR_DEC_GEN(15)
ADDR_DEC_GEN(16)
ADDR_DEC_GEN(17)
ADDR_DEC_GEN(18)
ADDR_DEC_GEN(19)
ADDR_DEC_GEN(20)
ADDR_DEC_GEN(21)
ADDR_DEC_GEN(22)
ADDR_DEC_GEN(23)
ADDR_DEC_GEN(24)
ADDR_DEC_GEN(25)
ADDR_DEC_GEN(26)
ADDR_DEC_GEN(27)
ADDR_DEC_GEN(28)
ADDR_DEC_GEN(29)
ADDR_DEC_GEN(30)
ADDR_DEC_GEN(31)
ADDR_DEC_GEN(32)
ADDR_DEC_GEN(33)
ADDR_DEC_GEN(34)
ADDR_DEC_GEN(35)
ADDR_DEC_GEN(36)
ADDR_DEC_GEN(37)
ADDR_DEC_GEN(38)
ADDR_DEC_REG_FALSE_GEN
MODE_RST_REG_COMP
BIT_GEN(0)
MODE_BMM_REG_COMP
BIT_GEN(0)
MODE_STM_REG_COMP
BIT_GEN(0)
MODE_AFM_REG_COMP
BIT_GEN(0)
MODE_FDE_REG_COMP
BIT_GEN(0)
MODE_TTTM_REG_COMP
BIT_GEN(0)
MODE_ROM_REG_COMP
BIT_GEN(0)
MODE_ACF_REG_COMP
BIT_GEN(0)
MODE_TSTM_REG_COMP
BIT_GEN(0)
MODE_RXBAM_REG_COMP
BIT_GEN(0)
MODE_TXBBM_REG_COMP
BIT_GEN(0)
MODE_SAM_REG_COMP
BIT_GEN(0)
MODE_ERFM_REG_COMP
BIT_GEN(0)
SETTINGS_RTRLE_REG_COMP
BIT_GEN(0)
SETTINGS_RTRTH_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
SETTINGS_ILBP_REG_COMP
BIT_GEN(0)
SETTINGS_ENA_REG_COMP
BIT_GEN(0)
SETTINGS_NISOFD_REG_COMP
BIT_GEN(0)
SETTINGS_PEX_REG_COMP
BIT_GEN(0)
SETTINGS_TBFBO_REG_COMP
BIT_GEN(0)
SETTINGS_FDRF_REG_COMP
BIT_GEN(0)
SETTINGS_PCHKE_REG_COMP
BIT_GEN(0)
COMMAND_RXRPMV_REG_COMP
BIT_GEN(0)
COMMAND_RRB_REG_COMP
BIT_GEN(0)
COMMAND_CDO_REG_COMP
BIT_GEN(0)
COMMAND_ERCRST_REG_COMP
BIT_GEN(0)
COMMAND_RXFCRST_REG_COMP
BIT_GEN(0)
COMMAND_TXFCRST_REG_COMP
BIT_GEN(0)
COMMAND_CPEXS_REG_COMP
BIT_GEN(0)
COMMAND_CRXPE_REG_COMP
BIT_GEN(0)
COMMAND_CTXPE_REG_COMP
BIT_GEN(0)
COMMAND_CTXDPE_REG_COMP
BIT_GEN(0)
INT_STAT_RXI_REG_COMP
BIT_GEN(0)
INT_STAT_TXI_REG_COMP
BIT_GEN(0)
INT_STAT_EWLI_REG_COMP
BIT_GEN(0)
INT_STAT_DOI_REG_COMP
BIT_GEN(0)
INT_STAT_FCSI_REG_COMP
BIT_GEN(0)
INT_STAT_ALI_REG_COMP
BIT_GEN(0)
INT_STAT_BEI_REG_COMP
BIT_GEN(0)
INT_STAT_OFI_REG_COMP
BIT_GEN(0)
INT_STAT_RXFI_REG_COMP
BIT_GEN(0)
INT_STAT_BSI_REG_COMP
BIT_GEN(0)
INT_STAT_RBNEI_REG_COMP
BIT_GEN(0)
INT_STAT_TXBHCI_REG_COMP
BIT_GEN(0)
INT_ENA_SET_INT_ENA_SET_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
INT_ENA_SET_INT_ENA_SET_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
INT_ENA_CLR_INT_ENA_CLR_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
INT_ENA_CLR_INT_ENA_CLR_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
INT_MASK_SET_INT_MASK_SET_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
INT_MASK_SET_INT_MASK_SET_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
INT_MASK_CLR_INT_MASK_CLR_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
INT_MASK_CLR_INT_MASK_CLR_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BTR_PROP_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BTR_PH1_SLICE_1_REG_COMP
BIT_GEN(0)
BTR_PH1_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BTR_PH2_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_PH2_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_BRP_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BTR_BRP_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_SJW_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BTR_FD_PROP_FD_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BTR_FD_PH1_FD_SLICE_1_REG_COMP
BIT_GEN(0)
BTR_FD_PH1_FD_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BTR_FD_PH2_FD_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_FD_PH2_FD_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BTR_FD_BRP_FD_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BTR_FD_BRP_FD_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_FD_SJW_FD_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
EWL_EW_LIMIT_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
ERP_ERP_LIMIT_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
CTR_PRES_CTPV_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
CTR_PRES_CTPV_SLICE_2_REG_COMP
BIT_GEN(0)
CTR_PRES_PTX_REG_COMP
BIT_GEN(0)
CTR_PRES_PRX_REG_COMP
BIT_GEN(0)
CTR_PRES_ENORM_REG_COMP
BIT_GEN(0)
CTR_PRES_EFD_REG_COMP
BIT_GEN(0)
FILTER_A_MASK_PRESENT_GEN_T
FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_A_MASK_BIT_MASK_A_VAL_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
FILTER_A_VAL_PRESENT_GEN_T
FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_A_VAL_BIT_VAL_A_VAL_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
FILTER_B_MASK_PRESENT_GEN_T
FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_B_MASK_BIT_MASK_B_VAL_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
FILTER_B_VAL_PRESENT_GEN_T
FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_B_VAL_BIT_VAL_B_VAL_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
FILTER_C_MASK_PRESENT_GEN_T
FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_C_MASK_BIT_MASK_C_VAL_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
FILTER_C_VAL_PRESENT_GEN_T
FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_C_VAL_BIT_VAL_C_VAL_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
FILTER_RAN_LOW_PRESENT_GEN_T
FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_RAN_LOW_BIT_RAN_LOW_VAL_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
FILTER_RAN_HIGH_PRESENT_GEN_T
FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
FILTER_CONTROL_FANB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FANE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FAFB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FAFE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FBNB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FBNE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FBFB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FBFE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FCNB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FCNE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FCFB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FCFE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FRNB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FRNE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FRFB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FRFE_REG_COMP
BIT_GEN(0)
RX_SETTINGS_RTSOP_REG_COMP
BIT_GEN(0)
RX_DATA_ACCESS_SIGNALLER_COMP
TX_COMMAND_TXCE_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXCR_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXCA_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB1_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB2_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB3_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB4_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB5_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB6_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB7_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB8_REG_COMP
BIT_GEN(0)
TX_PRIORITY_TXT1P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT2P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT3P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT4P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT5P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT6P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT7P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT8P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
SSP_CFG_SSP_OFFSET_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
SSP_CFG_SSP_SRC_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
FILTER_B_MASK_PRESENT_GEN_F
FILTER_B_VAL_PRESENT_GEN_F
FILTER_C_MASK_PRESENT_GEN_F
FILTER_C_VAL_PRESENT_GEN_F
FILTER_RAN_LOW_PRESENT_GEN_F
FILTER_RAN_HIGH_PRESENT_GEN_F
FILTER_A_MASK_PRESENT_GEN_F
FILTER_A_VAL_PRESENT_GEN_F
TEST_REGISTERS_GEN_TRUE
TEST_REGISTERS_REG_MAP_COMP
ADDRESS_DECODER_TEST_REGISTERS_COMP
ADDR_DEC_GEN(0)
ADDR_DEC_GEN(1)
ADDR_DEC_GEN(2)
ADDR_DEC_GEN(3)
ADDR_DEC_REG_FALSE_GEN
TST_CONTROL_TMAENA_REG_COMP
BIT_GEN(0)
TST_CONTROL_TWRSTB_REG_COMP
BIT_GEN(0)
TST_DEST_TST_ADDR_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_DEST_TST_ADDR_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_DEST_TST_MTGT_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
TST_WDATA_TST_WDATA_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_WDATA_TST_WDATA_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_WDATA_TST_WDATA_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_WDATA_TST_WDATA_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TXT_BUF_TEST_DATA_PADDING_GEN(0)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_TEST_DATA_PADDING_GEN(1)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_TEST_DATA_PADDING_GEN(2)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_PADDING_INDEX_GEN_FALSE
TXT_BUF_TEST_DATA_PADDING_GEN(3)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_PADDING_INDEX_GEN_FALSE
TXT_BUF_TEST_DATA_PADDING_GEN(4)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_PADDING_INDEX_GEN_FALSE
TXT_BUF_TEST_DATA_PADDING_GEN(5)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_PADDING_INDEX_GEN_FALSE
TXT_BUF_TEST_DATA_PADDING_GEN(6)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_PADDING_INDEX_GEN_FALSE
TXT_BUF_TEST_DATA_PADDING_GEN(7)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_PADDING_INDEX_GEN_FALSE
SOFT_RST_RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
GLOBAL_RST_RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
MT_2_TXT_BUFFS
MT_3_TXT_BUFFS
MT_4_TXT_BUFFS
MT_5_TXT_BUFFS
MT_6_TXT_BUFFS
MT_7_TXT_BUFFS
TXTB_FUNC_COV_GEN(0)
TXTB_FUNC_COV_GEN(1)
TXTB_FUNC_COV_GEN(2)
TXTB_FUNC_COV_GEN(3)
TXTB_FUNC_COV_GEN(4)
TXTB_FUNC_COV_GEN(5)
TXTB_FUNC_COV_GEN(6)
TXTB_FUNC_COV_GEN(7)
RX_BUFFER_INST
RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
RX_BUFFER_FSM_INST
ASSERTIONS_BLOCK
RX_BUFFER_POINTERS_INST
CLK_GATE_RX_BUFFER_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
RX_BUFFER_RAM_INST
RX_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_WRITE_INST
PARITY_CALCULATOR_READ_INST
PARITY_FALSE_GEN
TXTB_PARITY_TRUE_GEN
TXTB_PORT_A_PARITY_CALCULATOR_INST
TXT_BUF_COMP_GEN(0)
TXT_BUF_EVEN_GEN
TXT_BUFFER_EVEN_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_READ_INST
PARITY_FALSE_GEN
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(1)
TXT_BUF_ODD_GEN
TXT_BUFFER_ODD_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_READ_INST
PARITY_FALSE_GEN
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(2)
TXT_BUF_EVEN_GEN
TXT_BUFFER_EVEN_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_READ_INST
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(3)
TXT_BUF_ODD_GEN
TXT_BUFFER_ODD_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
G_TECH_FPGA
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_READ_INST
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(4)
TXT_BUF_EVEN_GEN
TXT_BUFFER_EVEN_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_READ_INST
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(5)
TXT_BUF_ODD_GEN
TXT_BUFFER_ODD_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_READ_INST
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(6)
TXT_BUF_EVEN_GEN
TXT_BUFFER_EVEN_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_READ_INST
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(7)
TXT_BUF_ODD_GEN
TXT_BUFFER_ODD_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_TRUE_GEN
PARITY_CALCULATOR_READ_INST
TXT_BUFFER_FSM_INST
TX_ARBITRATOR_INST
PRIORITY_DECODER_INST
L0_GEN(0)
L0_GEN(1)
L0_GEN(2)
L0_GEN(3)
L0_GEN(4)
L0_GEN(5)
L0_GEN(6)
L0_GEN(7)
FILL_ZEROES_GEN
TX_ARBITRATOR_FSM_INST
TXTB_PRIORITY_GEN(0)
TXTB_PRIORITY_EVEN_GEN
TXTB_PRIORITY_GEN(1)
TXTB_PRIORITY_ODD_GEN
TXTB_PRIORITY_GEN(2)
TXTB_PRIORITY_EVEN_GEN
TXTB_PRIORITY_GEN(3)
TXTB_PRIORITY_ODD_GEN
TXTB_PRIORITY_GEN(4)
TXTB_PRIORITY_EVEN_GEN
TXTB_PRIORITY_GEN(5)
TXTB_PRIORITY_ODD_GEN
TXTB_PRIORITY_GEN(6)
TXTB_PRIORITY_EVEN_GEN
TXTB_PRIORITY_GEN(7)
TXTB_PRIORITY_ODD_GEN
FRAME_FILTERS_INST
BIT_FILTER_A_INST
GEN_FILT_POS
GEN_FILT_NEG
BIT_FILTER_B_INST
GEN_FILT_POS
GEN_FILT_NEG
BIT_FILTER_C_INST
GEN_FILT_POS
GEN_FILT_NEG
RANGE_FILTER_INST
GEN_FILT_POS
GEN_FILTRAN_NEG
FILT_SUP_GEN_TRUE
FILT_SUP_GEN_FALSE
INT_MANAGER_INST
INT_MODULE_GEN(0)
INT_MODULE_INST
INT_MODULE_GEN(1)
INT_MODULE_INST
INT_MODULE_GEN(2)
INT_MODULE_INST
INT_MODULE_GEN(3)
INT_MODULE_INST
INT_MODULE_GEN(4)
INT_MODULE_INST
INT_MODULE_GEN(5)
INT_MODULE_INST
INT_MODULE_GEN(6)
INT_MODULE_INST
INT_MODULE_GEN(7)
INT_MODULE_INST
INT_MODULE_GEN(8)
INT_MODULE_INST
INT_MODULE_GEN(9)
INT_MODULE_INST
INT_MODULE_GEN(10)
INT_MODULE_INST
INT_MODULE_GEN(11)
INT_MODULE_INST
DFF_INT_OUTPUT_REG
CAN_CORE_INST
PROTOCOL_CONTROL_INST
ENDIAN_SWAPPER_TX_INST
SWAP_BY_GENERIC_TRUE_GEN
PROTOCOL_CONTROL_FSM_INST
DLC_DECODER_TX_INST
DLC_DECODER_RX_INST
DLC_DECODER_RX_INST_COMB
CONTROL_COUNTER_INST
REINTEGRATION_COUNTER_INST
RETRANSMITT_COUNTER_INST
ERR_DETECTOR_INST
ERR_PIPELINE_TRUE_GEN
TX_SHIFT_REG_INST
TX_SHIFT_REG_INST
RX_SHIFT_REG_INST
RX_SHIFT_RES_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
RX_SHIFT_CMD_GEN(0)
RX_SHIFT_CMD_GEN(1)
RX_SHIFT_CMD_GEN(2)
RX_SHIFT_CMD_GEN(3)
SHIFT_REG_BYTE_INST
BYTE_SHIFT_REG_GEN(0)
FIRST_BYTE_GEN
BYTE_SHIFT_REG_GEN(1)
NEXT_BYTES_GEN
BYTE_SHIFT_REG_GEN(2)
NEXT_BYTES_GEN
BYTE_SHIFT_REG_GEN(3)
NEXT_BYTES_GEN
OPERATION_CONTROL_INST
FAULT_CONFINEMENT_INST
FAULT_CONFINEMENT_FSM_INST
ERR_COUNTERS_INST
RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
FAULT_CONFINEMENT_RULES_INST
CAN_CRC_INST
CRC_CALC_15_INST
CRC_CALC_17_RX_INST
CRC_CALC_21_RX_INST
BIT_STUFFING_INST
DFF_ENA_REG
DFF_FIXED_STUFF_REG
DFF_DATA_OUT_REG
DFF_HALT_REG
BIT_DESTUFFING_INST
DFF_ENA_REG
DFF_FIXED_STUFF_REG
DFF_DESTUFFED_FLAG_REG
DFF_ERR_REG
DFF_PREV_VAL_REG
DFF_DATA_OUT_VAL_REG
BUS_TRAFFIC_CTRS_GEN
BUS_TRAFFIC_COUNTERS_INST
TX_CTR_REG_RST_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
RX_CTR_REG_RST_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
TRIGGER_MUX_INST
CRC_TRIG_TX_WBS_REG
CRC_DATA_RX_WBS_REG
NO_BUS_TRAFFIC_CTRS_GEN
PRESCALER_INST
BIT_TIME_CFG_CAPTURE_INST
SYNCHRONISATION_CHECKER_INST
BIT_SEGMENT_METER_NBT_INST
BIT_TIME_COUNTERS_NBT_INST
BIT_SEGMENT_METER_DBT_INST
BIT_TIME_COUNTERS_DBT_INST
SEGMENT_END_DETECTOR_INST
SEGM_END_REQ_CAPTURE(1)
SEGM_END_REQ_CAPTURE(2)
BIT_TIME_FSM_INST
TRIGGER_GENERATOR_INST
BUS_SAMPLING_INST
CAN_RX_SIG_SYNC_INST
TRV_DELAY_MEASUREMENT_INST
TRV_DELAY_RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
DATA_EDGE_DETECTOR_INST
SHIFT_REGS_RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
TX_TRIGGER_REG_INST
SSP_GENERATOR_INST
TX_DATA_CACHE_INST
BIT_ERR_DETECTOR_INST
SAMPLE_MUX_INST
TXTB_ASR_GEN(0)
TXTB_ASR_GEN(1)
TXTB_ASR_GEN(2)
TXTB_ASR_GEN(3)
TXTB_ASR_GEN(4)
TXTB_ASR_GEN(5)
TXTB_ASR_GEN(6)
TXTB_ASR_GEN(7)
TXTB_PARITY_FALSE_GEN
CTU_CAN_FD_VIP_INST
RESET_AGENT_INST
CLK_GEN_AGENT_INST
MEM_BUS_AGENT_INST
CS_GEN(0)
CS_GEN(1)
INTERRUPT_AGENT_INST
TIMESTAMP_AGENT_INST
TEST_PROBE_AGENT_INST
TEST_CONTROLLER_AGENT_INST
COMPLIANCE_TESTS_GEN
FEATURE_TEST_AGENT_GEN
FEATURE_TEST_AGENT_INST
TEST_NODE_INST
RST_SYNC_INST
MEMORY_REGISTERS_INST
TXTB_PORT_A_CS_GEN(0)
TXTB_PORT_A_CS_GEN(1)
TXTB_PORT_A_CS_GEN(2)
TXTB_PORT_A_CS_GEN(3)
CLK_GATE_CONTROL_REGS_COMP
G_TECH_ASIC
CLK_GATE_TEST_REGS_COMP
G_TECH_ASIC
CONTROL_REGISTERS_REG_MAP_COMP
ADDRESS_DECODER_CONTROL_REGISTERS_COMP
ADDR_DEC_GEN(0)
ADDR_DEC_GEN(1)
ADDR_DEC_GEN(2)
ADDR_DEC_GEN(3)
ADDR_DEC_GEN(4)
ADDR_DEC_GEN(5)
ADDR_DEC_GEN(6)
ADDR_DEC_GEN(7)
ADDR_DEC_GEN(8)
ADDR_DEC_GEN(9)
ADDR_DEC_GEN(10)
ADDR_DEC_GEN(11)
ADDR_DEC_GEN(12)
ADDR_DEC_GEN(13)
ADDR_DEC_GEN(14)
ADDR_DEC_GEN(15)
ADDR_DEC_GEN(16)
ADDR_DEC_GEN(17)
ADDR_DEC_GEN(18)
ADDR_DEC_GEN(19)
ADDR_DEC_GEN(20)
ADDR_DEC_GEN(21)
ADDR_DEC_GEN(22)
ADDR_DEC_GEN(23)
ADDR_DEC_GEN(24)
ADDR_DEC_GEN(25)
ADDR_DEC_GEN(26)
ADDR_DEC_GEN(27)
ADDR_DEC_GEN(28)
ADDR_DEC_GEN(29)
ADDR_DEC_GEN(30)
ADDR_DEC_GEN(31)
ADDR_DEC_GEN(32)
ADDR_DEC_GEN(33)
ADDR_DEC_GEN(34)
ADDR_DEC_GEN(35)
ADDR_DEC_GEN(36)
ADDR_DEC_GEN(37)
ADDR_DEC_GEN(38)
ADDR_DEC_REG_FALSE_GEN
MODE_RST_REG_COMP
BIT_GEN(0)
MODE_BMM_REG_COMP
BIT_GEN(0)
MODE_STM_REG_COMP
BIT_GEN(0)
MODE_AFM_REG_COMP
BIT_GEN(0)
MODE_FDE_REG_COMP
BIT_GEN(0)
MODE_TTTM_REG_COMP
BIT_GEN(0)
MODE_ROM_REG_COMP
BIT_GEN(0)
MODE_ACF_REG_COMP
BIT_GEN(0)
MODE_TSTM_REG_COMP
BIT_GEN(0)
MODE_RXBAM_REG_COMP
BIT_GEN(0)
MODE_TXBBM_REG_COMP
BIT_GEN(0)
MODE_SAM_REG_COMP
BIT_GEN(0)
MODE_ERFM_REG_COMP
BIT_GEN(0)
SETTINGS_RTRLE_REG_COMP
BIT_GEN(0)
SETTINGS_RTRTH_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
SETTINGS_ILBP_REG_COMP
BIT_GEN(0)
SETTINGS_ENA_REG_COMP
BIT_GEN(0)
SETTINGS_NISOFD_REG_COMP
BIT_GEN(0)
SETTINGS_PEX_REG_COMP
BIT_GEN(0)
SETTINGS_TBFBO_REG_COMP
BIT_GEN(0)
SETTINGS_FDRF_REG_COMP
BIT_GEN(0)
SETTINGS_PCHKE_REG_COMP
BIT_GEN(0)
COMMAND_RXRPMV_REG_COMP
BIT_GEN(0)
COMMAND_RRB_REG_COMP
BIT_GEN(0)
COMMAND_CDO_REG_COMP
BIT_GEN(0)
COMMAND_ERCRST_REG_COMP
BIT_GEN(0)
COMMAND_RXFCRST_REG_COMP
BIT_GEN(0)
COMMAND_TXFCRST_REG_COMP
BIT_GEN(0)
COMMAND_CPEXS_REG_COMP
BIT_GEN(0)
COMMAND_CRXPE_REG_COMP
BIT_GEN(0)
COMMAND_CTXPE_REG_COMP
BIT_GEN(0)
COMMAND_CTXDPE_REG_COMP
BIT_GEN(0)
INT_STAT_RXI_REG_COMP
BIT_GEN(0)
INT_STAT_TXI_REG_COMP
BIT_GEN(0)
INT_STAT_EWLI_REG_COMP
BIT_GEN(0)
INT_STAT_DOI_REG_COMP
BIT_GEN(0)
INT_STAT_FCSI_REG_COMP
BIT_GEN(0)
INT_STAT_ALI_REG_COMP
BIT_GEN(0)
INT_STAT_BEI_REG_COMP
BIT_GEN(0)
INT_STAT_OFI_REG_COMP
BIT_GEN(0)
INT_STAT_RXFI_REG_COMP
BIT_GEN(0)
INT_STAT_BSI_REG_COMP
BIT_GEN(0)
INT_STAT_RBNEI_REG_COMP
BIT_GEN(0)
INT_STAT_TXBHCI_REG_COMP
BIT_GEN(0)
INT_ENA_SET_INT_ENA_SET_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
INT_ENA_SET_INT_ENA_SET_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
INT_ENA_CLR_INT_ENA_CLR_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
INT_ENA_CLR_INT_ENA_CLR_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
INT_MASK_SET_INT_MASK_SET_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
INT_MASK_SET_INT_MASK_SET_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
INT_MASK_CLR_INT_MASK_CLR_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
INT_MASK_CLR_INT_MASK_CLR_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BTR_PROP_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BTR_PH1_SLICE_1_REG_COMP
BIT_GEN(0)
BTR_PH1_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BTR_PH2_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_PH2_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_BRP_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BTR_BRP_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_SJW_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BTR_FD_PROP_FD_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BTR_FD_PH1_FD_SLICE_1_REG_COMP
BIT_GEN(0)
BTR_FD_PH1_FD_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BTR_FD_PH2_FD_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_FD_PH2_FD_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BTR_FD_BRP_FD_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BTR_FD_BRP_FD_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BTR_FD_SJW_FD_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
EWL_EW_LIMIT_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
ERP_ERP_LIMIT_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
CTR_PRES_CTPV_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
CTR_PRES_CTPV_SLICE_2_REG_COMP
BIT_GEN(0)
CTR_PRES_PTX_REG_COMP
BIT_GEN(0)
CTR_PRES_PRX_REG_COMP
BIT_GEN(0)
CTR_PRES_ENORM_REG_COMP
BIT_GEN(0)
CTR_PRES_EFD_REG_COMP
BIT_GEN(0)
FILTER_A_MASK_PRESENT_GEN_F
FILTER_A_VAL_PRESENT_GEN_F
FILTER_B_MASK_PRESENT_GEN_F
FILTER_B_VAL_PRESENT_GEN_F
FILTER_C_MASK_PRESENT_GEN_F
FILTER_C_VAL_PRESENT_GEN_F
FILTER_RAN_LOW_PRESENT_GEN_F
FILTER_RAN_HIGH_PRESENT_GEN_F
FILTER_CONTROL_FANB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FANE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FAFB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FAFE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FBNB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FBNE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FBFB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FBFE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FCNB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FCNE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FCFB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FCFE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FRNB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FRNE_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FRFB_REG_COMP
BIT_GEN(0)
FILTER_CONTROL_FRFE_REG_COMP
BIT_GEN(0)
RX_SETTINGS_RTSOP_REG_COMP
BIT_GEN(0)
RX_DATA_ACCESS_SIGNALLER_COMP
TX_COMMAND_TXCE_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXCR_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXCA_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB1_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB2_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB3_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB4_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB5_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB6_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB7_REG_COMP
BIT_GEN(0)
TX_COMMAND_TXB8_REG_COMP
BIT_GEN(0)
TX_PRIORITY_TXT1P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT2P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT3P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT4P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT5P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT6P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT7P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
TX_PRIORITY_TXT8P_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
SSP_CFG_SSP_OFFSET_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
SSP_CFG_SSP_SRC_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
TEST_REGISTERS_GEN_TRUE
TEST_REGISTERS_REG_MAP_COMP
ADDRESS_DECODER_TEST_REGISTERS_COMP
ADDR_DEC_GEN(0)
ADDR_DEC_GEN(1)
ADDR_DEC_GEN(2)
ADDR_DEC_GEN(3)
ADDR_DEC_REG_FALSE_GEN
TST_CONTROL_TMAENA_REG_COMP
BIT_GEN(0)
TST_CONTROL_TWRSTB_REG_COMP
BIT_GEN(0)
TST_DEST_TST_ADDR_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_DEST_TST_ADDR_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_DEST_TST_MTGT_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
TST_WDATA_TST_WDATA_SLICE_1_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_WDATA_TST_WDATA_SLICE_2_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_WDATA_TST_WDATA_SLICE_3_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TST_WDATA_TST_WDATA_SLICE_4_REG_COMP
BIT_GEN(0)
BIT_GEN(1)
BIT_GEN(2)
BIT_GEN(3)
BIT_GEN(4)
BIT_GEN(5)
BIT_GEN(6)
BIT_GEN(7)
TXT_BUF_TEST_DATA_PADDING_GEN(0)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_TEST_DATA_PADDING_GEN(1)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_TEST_DATA_PADDING_GEN(2)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_TEST_DATA_PADDING_GEN(3)
TXT_BUF_PADDING_INDEX_GEN_TRUE
TXT_BUF_TEST_DATA_PADDING_GEN(4)
TXT_BUF_PADDING_INDEX_GEN_FALSE
TXT_BUF_TEST_DATA_PADDING_GEN(5)
TXT_BUF_PADDING_INDEX_GEN_FALSE
TXT_BUF_TEST_DATA_PADDING_GEN(6)
TXT_BUF_PADDING_INDEX_GEN_FALSE
TXT_BUF_TEST_DATA_PADDING_GEN(7)
TXT_BUF_PADDING_INDEX_GEN_FALSE
SOFT_RST_RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
GLOBAL_RST_RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
MT_2_TXT_BUFFS
MT_3_TXT_BUFFS
TXTB_FUNC_COV_GEN(0)
TXTB_FUNC_COV_GEN(1)
TXTB_FUNC_COV_GEN(2)
TXTB_FUNC_COV_GEN(3)
RX_BUFFER_INST
RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
RX_BUFFER_FSM_INST
ASSERTIONS_BLOCK
RX_BUFFER_POINTERS_INST
CLK_GATE_RX_BUFFER_RAM_COMP
G_TECH_ASIC
RX_BUFFER_RAM_INST
RX_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_FALSE_GEN
TXTB_PARITY_FALSE_GEN
TXT_BUF_COMP_GEN(0)
TXT_BUF_EVEN_GEN
TXT_BUFFER_EVEN_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_FALSE_GEN
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(1)
TXT_BUF_ODD_GEN
TXT_BUFFER_ODD_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_FALSE_GEN
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(2)
TXT_BUF_EVEN_GEN
TXT_BUFFER_EVEN_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_FALSE_GEN
TXT_BUFFER_FSM_INST
TXT_BUF_COMP_GEN(3)
TXT_BUF_ODD_GEN
TXT_BUFFER_ODD_INST
CLK_GATE_TXT_BUFFER_RAM_COMP
G_TECH_ASIC
TXT_BUFFER_RAM_INST
TXT_BUF_RAM_INST
BYTE_GEN(0)
BYTE_GEN(1)
BYTE_GEN(2)
BYTE_GEN(3)
RAM_RST_FALSE_GEN
SYNC_READ_GEN
PARITY_FALSE_GEN
TXT_BUFFER_FSM_INST
TX_ARBITRATOR_INST
PRIORITY_DECODER_INST
L0_GEN(0)
L0_GEN(1)
L0_GEN(2)
L0_GEN(3)
FILL_ZEROES_GEN
TX_ARBITRATOR_FSM_INST
TXTB_PRIORITY_GEN(0)
TXTB_PRIORITY_EVEN_GEN
TXTB_PRIORITY_GEN(1)
TXTB_PRIORITY_ODD_GEN
TXTB_PRIORITY_GEN(2)
TXTB_PRIORITY_EVEN_GEN
TXTB_PRIORITY_GEN(3)
TXTB_PRIORITY_ODD_GEN
FRAME_FILTERS_INST
BIT_FILTER_A_INST
GEN_FILT_NEG
BIT_FILTER_B_INST
GEN_FILT_NEG
BIT_FILTER_C_INST
GEN_FILT_NEG
RANGE_FILTER_INST
GEN_FILTRAN_NEG
FILT_SUP_GEN_FALSE
INT_MANAGER_INST
INT_MODULE_GEN(0)
INT_MODULE_INST
INT_MODULE_GEN(1)
INT_MODULE_INST
INT_MODULE_GEN(2)
INT_MODULE_INST
INT_MODULE_GEN(3)
INT_MODULE_INST
INT_MODULE_GEN(4)
INT_MODULE_INST
INT_MODULE_GEN(5)
INT_MODULE_INST
INT_MODULE_GEN(6)
INT_MODULE_INST
INT_MODULE_GEN(7)
INT_MODULE_INST
INT_MODULE_GEN(8)
INT_MODULE_INST
INT_MODULE_GEN(9)
INT_MODULE_INST
INT_MODULE_GEN(10)
INT_MODULE_INST
INT_MODULE_GEN(11)
INT_MODULE_INST
DFF_INT_OUTPUT_REG
CAN_CORE_INST
PROTOCOL_CONTROL_INST
ENDIAN_SWAPPER_TX_INST
SWAP_BY_GENERIC_TRUE_GEN
PROTOCOL_CONTROL_FSM_INST
DLC_DECODER_TX_INST
DLC_DECODER_RX_INST
DLC_DECODER_RX_INST_COMB
CONTROL_COUNTER_INST
REINTEGRATION_COUNTER_INST
RETRANSMITT_COUNTER_INST
ERR_DETECTOR_INST
ERR_PIPELINE_TRUE_GEN
TX_SHIFT_REG_INST
TX_SHIFT_REG_INST
RX_SHIFT_REG_INST
RX_SHIFT_RES_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
RX_SHIFT_CMD_GEN(0)
RX_SHIFT_CMD_GEN(1)
RX_SHIFT_CMD_GEN(2)
RX_SHIFT_CMD_GEN(3)
SHIFT_REG_BYTE_INST
BYTE_SHIFT_REG_GEN(0)
FIRST_BYTE_GEN
BYTE_SHIFT_REG_GEN(1)
NEXT_BYTES_GEN
BYTE_SHIFT_REG_GEN(2)
NEXT_BYTES_GEN
BYTE_SHIFT_REG_GEN(3)
NEXT_BYTES_GEN
OPERATION_CONTROL_INST
FAULT_CONFINEMENT_INST
FAULT_CONFINEMENT_FSM_INST
ERR_COUNTERS_INST
RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
FAULT_CONFINEMENT_RULES_INST
CAN_CRC_INST
CRC_CALC_15_INST
CRC_CALC_17_RX_INST
CRC_CALC_21_RX_INST
BIT_STUFFING_INST
DFF_ENA_REG
DFF_FIXED_STUFF_REG
DFF_DATA_OUT_REG
DFF_HALT_REG
BIT_DESTUFFING_INST
DFF_ENA_REG
DFF_FIXED_STUFF_REG
DFF_DESTUFFED_FLAG_REG
DFF_ERR_REG
DFF_PREV_VAL_REG
DFF_DATA_OUT_VAL_REG
BUS_TRAFFIC_CTRS_GEN
BUS_TRAFFIC_COUNTERS_INST
TX_CTR_REG_RST_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
RX_CTR_REG_RST_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
TRIGGER_MUX_INST
CRC_TRIG_TX_WBS_REG
CRC_DATA_RX_WBS_REG
PRESCALER_INST
BIT_TIME_CFG_CAPTURE_INST
SYNCHRONISATION_CHECKER_INST
BIT_SEGMENT_METER_NBT_INST
BIT_TIME_COUNTERS_NBT_INST
BIT_SEGMENT_METER_DBT_INST
BIT_TIME_COUNTERS_DBT_INST
SEGMENT_END_DETECTOR_INST
SEGM_END_REQ_CAPTURE(1)
SEGM_END_REQ_CAPTURE(2)
BIT_TIME_FSM_INST
TRIGGER_GENERATOR_INST
BUS_SAMPLING_INST
CAN_RX_SIG_SYNC_INST
TRV_DELAY_MEASUREMENT_INST
TRV_DELAY_RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
DATA_EDGE_DETECTOR_INST
SHIFT_REGS_RST_REG_INST
RX_SHIFT_RES_REG_INST
MUX2_RES_TST_INST
TX_TRIGGER_REG_INST
SSP_GENERATOR_INST
TX_DATA_CACHE_INST
BIT_ERR_DETECTOR_INST
SAMPLE_MUX_INST
TXTB_ASR_GEN(0)
TXTB_ASR_GEN(1)
TXTB_ASR_GEN(2)
TXTB_ASR_GEN(3)
I_TX_DELAY_DUT
I_SDV
I_TX_DELAY_TEST_NODE
I_SDV
REFERENCE_TEST_AGENT_INST
G_FUNC_COV
FUNC_COV_AGENT_INST
FUNC_COV_CAN_CORE_INST
FUNC_COV_PRESCALER_INST
FUNC_COV_PRESCALER_NBT_INST
FUNC_COV_PRESCALER_DBT_INST
FUNC_COV_BUS_SAMPLING_INST
FUNC_COV_RX_BUFFER_INST
FUNC_COV_TX_ARBITRATOR_INST
G_EACH_BUF(0)
FUNC_COV_TX_ARBITRATOR_PER_BUF_INST
G_EACH_BUF(1)
FUNC_COV_TX_ARBITRATOR_PER_BUF_INST
G_EACH_BUF(2)
FUNC_COV_TX_ARBITRATOR_PER_BUF_INST
G_EACH_BUF(3)
FUNC_COV_TX_ARBITRATOR_PER_BUF_INST
G_EACH_BUF(4)
FUNC_COV_TX_ARBITRATOR_PER_BUF_INST
G_EACH_BUF(5)
FUNC_COV_TX_ARBITRATOR_PER_BUF_INST
G_EACH_BUF(6)
FUNC_COV_TX_ARBITRATOR_PER_BUF_INST
G_EACH_BUF(7)
FUNC_COV_TX_ARBITRATOR_PER_BUF_INST
G_EACH_BUF(0)
TXT_BUF_EVEN_GEN
FUNC_COV_TXT_BUFFER_EVEN_INST
G_EACH_BUF(1)
TXT_BUF_ODD_GEN
FUNC_COV_TXT_BUFFER_ODD_INST
G_EACH_BUF(2)
TXT_BUF_EVEN_GEN
FUNC_COV_TXT_BUFFER_EVEN_INST
G_EACH_BUF(3)
TXT_BUF_ODD_GEN
FUNC_COV_TXT_BUFFER_ODD_INST
G_EACH_BUF(4)
TXT_BUF_EVEN_GEN
FUNC_COV_TXT_BUFFER_EVEN_INST
G_EACH_BUF(5)
TXT_BUF_ODD_GEN
FUNC_COV_TXT_BUFFER_ODD_INST
G_EACH_BUF(6)
TXT_BUF_EVEN_GEN
FUNC_COV_TXT_BUFFER_EVEN_INST
G_EACH_BUF(7)
TXT_BUF_ODD_GEN
FUNC_COV_TXT_BUFFER_ODD_INST
CAN_AGENT_GEN
COMPLIANCE_AGENT_INST
WATCHDOG
Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXTB_ASR_GEN(3)
File:
/builds/canbus/ctucanfd_ip_core/src/can_top_level.vhd
Current Instance:
Instance
Statement
Branch
Toggle
Expression
FSM state
Functional
Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXTB_ASR_GEN(3)
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
Details:
The limit of printed items was reached (5000). Total 261158 items are not displayed.
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Branch
Toggle
Expression
FSM state
Functional
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