CAN bus CTU FEE Projects

The list of CAN bus related projects at Faculty of Electrical Engineering at Czech Technical University in Prague


The VHDL open-source CAN FD core project.

Project pages:

Documentation and testing:

Integration with FPGA SoCs and boards


OpenCores SJA-1000 FD Tol

OpenCores SJA-1000 controller modified to ignore CAN FD frames which allows it to coexists and send frames on network with CAN FD traffic. The core is packed as a Xilinx Vivado component.

Project pages:

CAN Bus Channels Mutual Latency Testing

Project done in cooperation with Voklswagen Research and SocketCAN Author Oliver Hartkopp.

Description of the project boards, hardware and VHDL desig.

CAN/CAN FD Latency Tester utility

List of more CTU FEE CAN projects